1. Field of the Invention
This invention relates to a digital data transmission system wherein an error correction code of the product sign format is appended to transmitted data and NRZL-NRZI conversion is performed.
2. Description of the Prior Art
Conventionally, a data recorder conforming to the ANSI ID-1 format (Third Draft PROPOSED AMERICAN NATIONAL STANDARD 19 mm TYPE ID-1 INSTRUMENTATION DIGITAL CASSETTE FORMAT X3B6-88-12 Project 592-D 1988-03-22) is known as a recording and reproducing device which effects high density recording of information data.
In such a data recorder, an error correction code of the product sign format employing a Reed-Solomon code is appended to information data and such information data are recorded on a magnetic tape. Upon reproduction error detection and correction are performed to detect errors encountered in transmission and to correct the same.
Such a data recorder is generally described below.
FIG. 1 illustrates a record pattern which is recorded on a magnetic tape by means of a data recorder conforming to the ID-1 format. The record pattern shown includes a longitudinal annotation track ANN on which annotations are recorded and oblique data tracks TR1, TR2, TR3, . . . on which information data are recorded with one sector formed on each track. Individual data tracks are azimuth recorded in an alternating relationship. The record pattern further includes a control track CTL on which control signals are recorded, and a time code track TC on which time codes are recorded.
Commonly construction of the data tracks TR1, TR2, TR3, . . . is as illustrated in FIG. 2. In particular, each of the data tracks TR corresponds to one sector SEC and consists of a preamble portion PR, a data record portion DT and a postamble portion PS. The preamble portion PR corresponds to a lower side portion of a data track oriented is a slanted inclining relationship on the magnetic tape, as illustrated in FIG. 1
The preamble portion PR consists of a rising sequence RUS having a length of 20 bytes, a synchronization code SYNC.sub.PR and sector identification data ID.sub.sec1 each having a length of 4 bytes, and auxiliary data DT.sub.AUX having a length of 6 bytes.
The subsequent data record portion DT, on which information data are recorded, consists of 256 synchronization blocks BLK (BLK.sub.0, BLK.sub.1, BLK.sub.2, . . . and BLK.sub.255). Each of the synchronization blocks BLK consists of a block synchronization code SYNC.sub.BLK having a length of 4 bytes, block identification data ID.sub.B having a length of one byte, inner data (data obtained by inner decoding of input information data which had previously undergone outer decoding) DI having length of 153 bytes, and a parity code RI in the form of a Reed-Solomon code having a length of 8 bytes.
The postamble portion PS of each of the data tracks consists of a synchronization code SYNC.sub.PS and sector identification data ID.sub.SEC2 each having a length of 4 bytes.
FIG. 3 illustrates the recording system of a data recorder conforming to ID-1 format. In the recording system 1, an error correction code of the product sign format is appended to input information data, and the information data thus obtained is recorded onto a magnetic tape.
The operation of individual elements of the recording system 1 is as follows.
First, information data DT.sub.use are first provided to an outer code generating circuit 2.
Using a predetermined generating function, the outer code generating circuit 2 generates as outer parity codes RO.sub.0 to RO.sub.305 each consisting of a 10 byte Reed-Solomon code for the individual data blocks of the input information data DT.sub.USE. The individual data blocks each include 118 bytes. The outer code generating circuit 2 then appends the outer codes to the ends of the individual blocks as shown in FIG. 4 and outputs them as outer data blocks DO. The outer data blocks DO are transmitted to a memory 4 by way of a first multiplexer 3.
Construction of the memory 4 and an array of data in the memory 4 are illustrated in FIG. 5. As shown in FIG. 5, the memory 4 includes two memories MEM1 and MEM2 wherein each row includes 154 bytes and each column includes 128 bytes. Outer data blocks DO.sub.0 to DO.sub.52, that is, 153 blocks successively inputted to the memory written into the memory MEM1 while outer data blocks DO.sub.153 to DO.sub.305, that is, the next 153 blocks subsequentially input to the memory 4 are written into the other memory MEM2. The outer data blocks are written in memories MEM1 and MEM2 so that each outer data block occupies one column of memory space. Since the information component of one outer data block consists of 118 bytes and 153 blocks of information data are written into each of the memories MEM1 and MEM2, the memory 4 stores 118.times.153.times.2 bytes, or 36,108 bytes of information data therein.
The order of writing the outer data blocks in each column of the memories MEM1 and MEM2 is indicated by an arrow A in FIG. 5, and each 10 byte outer error code is written last in each column of the memories MEM1 and MEM2.
Data block identification data ID.sub.B which are generated by an identification data generating circuit 5 and serve as data for the identification of each row in the memories MEM1 and MEM2 are also transmitted to the memory 4 by way of the first multiplexer 3. Even-numbered data block identification data ID.sub.BE and odd-numbered data block identification ID.sub.BO are written in the direction indicated by arrow A into the memories MEM1 and MEM2, respectively.
The data block identification data ID.sub.B serve as identification data for subsequent inner coding of the outer data blocks which is performed on each row of data in the memories MEM1 and MEM2 in contrast to outer coding, which as described above, is executed in accordance with each column of memories MEM1 and MEM2.
Data written in the memories MEM1 and MEM2 are read front each row of the memories in an order indicated by an arrow B in FIG. 5. Reading of the individual rows is executed alternately from the memories MEM1 and MEM2 in an order corresponding to the data block identification data ID.sub.b (00, 01, 02, 03, . . . ).
Data read out from the memories MEM1 and MEM2 are input to an inner code generating circuit 6.
Using a predetermined generating function, the inner code generating circuit 6 generates inner parity codes RI.sub.0 to RI.sub.255 each consisting of an byte Reed-Solomon code for the individual inner data blocks input thereto. The inner code generating circuit 6 appends the inner codes to ends of the individual data blocks and outputs them as inner data blocks DI.sub.0 to DI.sub.255, as shown in FIG. 6, to a second multiplexer 7.
The second multiplexer 7 successively selects and outputs preamble data PR and postamble data PS produced by a preamble portion and postamble portion generating circuit 8, and inner data blocks DI.sub.0 to DI.sub.255 output from the inner code generating circuit 6. The order of the resulting output data is: preamble data PR, inner data block DI.sub.0 to DI.sub.255 and postamble data PS.
The output of the second multiplexer 7 is supplied to a data randomizer 9.
In order to randomize the data, the data randomizer 9 performs an exclusive OR operation between each byte of data input thereto and predetermined data.
Such randomized data are provided to an 8-9 modulating circuit 10.
The 8-9 modulating circuit 10 converts 8-bit data into 9-bit data in order to remove a dc component from a signal to be recorded onto a magnetic tape. The conversion is performed as follows:
In particular, 9-bit data of two kinds are predefined for each of the 256 possible values of 8 bit input data in accordance with the ID-1 format. The two kinds of 9-bit data are such that in CDS (Codeword Digital Sums) thereof are of opposite polarity. The 8-9 modulating circuit 10 monitors the DSV (Digital Sum Variation) of 9-bit data output in response to input data and selects the two kinds of 9-bit data such that the value of the DSV converges to zero. In this memory 8-bit input data are converted into 9-bit dc free data.
It is to be noted that the 8-9 modulating circuit 10 includes a circuit for converting the format of input data of NRZL (Non-Return-to-Zero-Level) into NRZI (Non-Return-to-Zero-Inverse) data.
An output of the 8-9 modulating circuit 10, that is, 9-bit NRZI data is supplied to a third multiplexer 11.
The third multiplexer 11 adds to each of the inner data blocks DI.sub.0 to DI.sub.255 a fixed synchronization code SYNC.sub.B having a length of 4 bytes generated by a synchronization code generating circuit 12 to form a synchronization block BLK.sub.0 to BLK.sub.255. A code pattern of the synchronization code SYNC.sub.B is prescribed by the ID-1 format, and it is also prescribed that a pattern recorded on a magnetic tape must maintain such code pattern.
Data obtained by the processing described above is illustrated in the maps shown in FIG. 7. An output of the third multiplexer 11 provides a data array which is obtained by scanning the maps MAP1 and MAP2 in a horizontal direction. Details of the data array are shown in FIG. 2.
The output of the third multiplexer 11 is supplied to a parallel/serial converting circuit 13.
The parallel/serial converting circuit 13 converts parallel data of the preamble portion PR, synchronization blocks BLK.sub.0 to BLK.sub.255 and postamble portion PS provided thereto into serial data S.sub.REC.
The serial data S.sub.REC are amplified by a recording and amplifying circuit 14 and then supplied as a recording signal to a magnetic head 16 which scans a magnetic tape 15 to record the signal on the magnetic tape 15. Consequently, data tracks TR ( . . . , TR1, TR2, TR3, TR4, . . . ) as shown in FIG. 1 are formed on the magnetic tape 15.
The recording system 1 of the data recorder is structured in this manner such that it adds an error correction code to desired information data DT.sub.USE in accordance with the Reed-Solomon product sign format to be record with the information data.
The information data DT.sub.USE recorded on the magnetic tape 14 by the recording system 1 of the data recorder in this manner are reproduced by a reproducing system 20 of the data recorder shown in FIG. 8.
The reproducing system 20 executes signal processing that is substantially the reverse of that executed by the recording system 1.
In particular, in the reproducing system 20 of the data recorder, record tracks TR ( . . . , TR1, TR2, TR3, TR4, . . . ) on a magnetic tape 15 are read out as a reproduction signal S.sub.PB using a magnetic head 16 and supplied to a reproducing and amplifying circuit 21.
The reproducing and amplifying circuit 21 includes an equalizer and binary digitizing circuit which binary digitizes the reproduction signal S.sub.PB input thereto into reproduction digital data DT.sub.PB which are provided to a succeeding serial/parallel converting circuit 22.
The serial/parallel converting circuit 22 converts the serial reproduction digital data DT.sub.PB into 9-bit parallel data DT.sub.PR.
A synchronization code detecting circuit 23 detects a synchronization code SYNC.sub.B from the parallel data DT.sub.PR and identifies each synchronization block in accordance with such synchronization code SYNC.sub.B. The synchronization code detecting circuit 23 includes a circuit for converting parallel data DT.sub.PR of the NRZI format into the NRZL format.
An output of the synchronization code detecting circuit 23 is inputted an 8-9 demodulating circuit 24. The 8-9 demodulating circuit 24 demodulates data which have been converted from 8-bit data into 9-bit data for eliminating its DC component and then converts it back into 8-bit data. The 8-9 demodulating circuit 24 includes a ROM (Read Only Memory) and converts data from 9 bits into 8 bits by map retrieval processing.
Data demodulated into 8-bits are derandomized by a derandomizer 25 in a manner that is the inverse of the randomizing executed by the recording system 1. Derandomization is accomplished by performing an exclusive or operation between data input to the derandomizer 25 and the same predetermined data used for the randomizing processing.
An inner code error detecting circuit 26 then executes error detection and correction using 8-byte inner codes RI.sub.0 to RI.sub.255 appended to the individual inner data blocks DI.sub.0 to DI.sub.255 among the identified synchronization blocks.
After inner code error detection and corrections is performed the are written in a memory 28 having the same construction as the memory 4 of the recording system 1 shown in FIG. 5 such that each block of data will fill one row of memory space. Block identification data ID.sub.B appended to individual blocks by identification data generating circuit 5 are detected by an identification data detecting circuit 27.Inner data blocks are written to memory 28 in an order similar to the order of reading inner data blocks from the memory 4 of the recording system 1, and writing is executed for each row alternately into memories MEM1 and MEM2 in accordance with block identification data.
Inner data blocks written to the memories MEM1 and MEM2 of the memory 28 are subsequently read out column by column in the same order as writing outer data blocks to the memory 4 of the recording system 1. As a result, outer data blocks DO.sub.0 to DO.sub.306 having a length of 128 bytes are obtained.
An outer code error detecting and correcting circuit 29 executes error detection and correction in accordance with outer codes RO.sub.0 to RO.sub.306 appended to the individual outer data blocks DO.sub.0 to DO.sub.306 output from the memory 28.
Information data DT.sub.USE recorded on the magnetic tape 15 are reproduced in this manner.
A data recorder having the construction described above has problems in actually receiving, recording and reproducing information data. Accordingly, it is difficult to obtain a data recorder with a high degree of accuracy.
The 8-9 modulating circuit used in the recording system 1 of the data recorder described above is disclosed in U.S. Pat. No. 4,520,346 and is generally constituted as shown in FIG. 9.
In particular, in the 8-9 modulating circuit 10, input data DT.sub.NRZL in the form of an NRZL (non-return-to-zero-level) code of 8 bits are inputted to a code converting circuit 102 and a CDS (Codeword Digital Sum) converting circuit 103 by way of an input register circuit 101.
The code converting circuit 102 may be constituted by a ROM (read only memory) in which are stored contents of a code conversion table, such as table 3. Randomized 8-bit Byte to 9-bit NRZL Word Mapping pages 15 to 20in the ID-1 format. Code word data DT.sub.CODE obtained by conversion of input data DT.sub.NRZL into an NRZL code of 9 bits are read out from a memory address of the code converting circuit 102 corresponding to input data DT.sub.NRZL and a CDS selection signal C.sub.CDS inputted thereto from a controlling circuit 104.
The code word data DT.sub.CODE are once converted into serial data S.sub.CODE by means of a parallel to serial converting circuit 105 and then inputted to an NRZL/NRZI (non-return-to-zero-level/non-return-to-zero-inverse) converting circuit 106 at which the Serial data code S.sub.CODE are NRZL/NRZI converted, and serial output data S.sub.NRZI in the form of an NRZI code are sent out from the NRZL/NRZI converting circuit 106.
The CDS converting circuit 103 may also be constituted by a ROM in which are stored contents of a CDS conversion table (Table 3, Randomized 8-bit Byte to 9-bit NRZL Word mapping appealing (pages 15 to 20) in the ID-1 format) similarly to the code converting circuit 102. And CDS data D.sub.CDS are read out from a memory address of the CDS converting circuit 103 corresponding to input data DT.sub.NRZL and a CDS selection signal C.sub.CDS inputted thereto from the controlling circuit 104. The CDS data D.sub.CDS thus read out from circuit 103 are sent to an adding/subtracting circuit 107.
The adding/subtracting circuit 107 adds or subtracts CDS data D.sub.CDS to or from DSV (Digital Sum Variation) data D.sub.DSV in response to an addition/subtraction controlling signal C.sub.AS inputted thereto from the controlling circuit 104. The result of such calculation is added cumulatively at an accumulator circuit 108. Then, DSV data D.sub.DSV obtained by such cumulative addition are inputted from the accumulator circuit 108 to the adding/subtracting circuit 107.
Meanwhile, inputted to the controlling circuit 104 are a CDS signal S.sub.CDS from the CDS converting circuit 103, A DSV signal S.sub.DSV in the form of a code bit of DSV data D.sub.DSV from the accumulator circuit 108 and a last bit signal S.sub.NRZI of code word data DT.sub.CODE after NRZL/NRZI conversion by the NRZL/NRZI converting circuit 106. Then, the controlling circuit 104 sends out a CDS selection signal C.sub.CDS for the code converting circuit 102 and the CDS converting circuit 103 in accordance with a a control table, such as, Table 4, 9-bit NRZL Word Selection appearing at page 21, and Table 5, DSV Calculation Using Preamble Run-up and Sync Pattern at page 22 of the ID-1 format. The controlling circuit 104 further sends out an addition/subtraction controlling signal C.sub.AS for the adding/subtracting circuit 107.
It is to be noted that, in the 8-9 modulating circuit 10 of FIG. 9, a reset signal S.sub.RST is inputted to the controlling circuit 104 and the accumulator circuit 108 so that the entire 8-9 modulating circuit 10 may be initialized for each sector SEC.
In the ID-1 format, magnetization patterns are individually specified for the rising sequence RUS of the preamble portion PR, the synchronization codes SYNC.sub.PR and SYNC.sub.PS of the preamble portion PR and postamble portion PS and the block synchronization code SYNC.sub.BLK of synchronization block BLK.
In particular, the rising sequence RUS of the preamble portion PR is specified to have a magnetization pattern which consists of the 18-bit "001110001 110001110" repeated 10 times from the LSB (least significant bit), while the synchronization codes SYNC.sub.PR and SYNC.sub.PS of the preamble portion PR and postamble portion PS are specified to have another magnetization pattern represented by "000011001 111111110 010111000 000001101" in order from the LSB, and the block synchronization code SYNC.sub.BLK of the synchronization block BLK is specified to have still another magnetization pattern represented by "111100110 000000001 101000111 111110010" in order from the LSB, as in the 5.4 Helical Record Content. Format, Synchronization, and Recording Method at pages 7 to 11.
In the 8-9 modulating circuit 10 having the circuit construction described above, the polarity of serial output data DT.sub.NRZI obtained by NRZL/NRZI conversion of input data DT.sub.NRZL is specified by the polarity of the last bit S.sub.NRZI of serial output data DT.sub.NRZI immediately preceding the current serial output data. Accordingly, a problem arises in that the synchronization code SYNC.sub.PR or SYNC.sub.PS or the block synchronization code SYNC.sub.BLK cannot be recorded with a specified magnetization pattern.
Consequently, although in the recording system 1 (FIG. 3) of the data recorder, a synchronization code SYNC.sub.PR or SYNC.sub.PS or a block synchronization code SYNC.sub.BLK from the synchronization code generating circuit 12 is combined at a predetermined timing with data after 8-9 modulation from the 8-9 modulating circuit 10, there is the further problem that the polarity data after NRZL/NRZI conversion becomes indefinite and cannot be reproduced by a reproducing system.
On the other hand, the inner code error detecting and correcting circuit 26 of the reproducing system 20 (FIG. 8) of the data recorder actually operates in the following manner. Identification data ID.sub.B, synchronization block data DT.sub.BLK and a parity code RI are written in that order at an address corresponding to each of identification data ID.sub.B of those synchronization blocks BLK which are free from errors or the errors of which have been corrected. On the other hand, only an inner code error flag FLG.sub.IN is added to each of those synchronization blocks BLK which cannot be corrected to eliminate an error, and writing of such synchronization blocks BLK into the memory is suspended.
The outer code error detecting and correcting circuit 29 successively reads the two memories MEM1 and MEM2 of the memory 28, into which an output of the inner code error detecting and correcting circuit 26 has been written, for each 128 bytes in the column direction and executes error detection and correction processing using an outer code. Recorded information data DT.sub.USE are reproduced in this manner.
If, in the reproducing system 20 of the data recorder described above, writing into the memory of a synchronization block BLK for which an error cannot be corrected is suspended by the inner code error detecting and correcting circuit 26, then in case an error takes place at a portion other than the synchronization block data DT.sub.BLK, that is, at the synchronization code SYNC.sub.BLK, the identification data ID.sub.B or the parity code RI and this makes correction of an error impossible, the synchronization block data DT.sub.BLK which are not actually in error will also not be written into the memory. Consequently, the correct synchronization block data DT.sub.BLK cannot be sent to the outer code error detecting and correcting circuit 29. As a result, there is a problem in that the outer code error detecting and correcting circuit 29 may also make correction of an error impossible.
In the even that the inner code error detecting and correcting circuit 26 corrects an error of a synchronization block BLK in error and the identification data ID.sub.B of the synchronization block BLK are also in error, the synchronization block BLK is written as a correct synchronization block BLK at a wrong memory address. Accordingly, there is a problem in that, in case the outer code error detecting and correcting circuit 29 executes an erasure calculation as a result, further correction will be erroneously effected.
In the event that data of all "0"s are inputted, due to a dropout on the magnetic tape 15 or the like, for a synchronization block BLK wherein the identification data ID.sub.B have a value other than "00", a synchronization block BLK of all "0"s is written as correct data at an address of the memory for which the identification data ID.sub.B have the value "00". Accordingly, there is a problem in that, if the outer code error detecting and correcting circuit 29 makes an erasure calculation, further correction will will be erroneously effected as described above.